The present invention relates to a MOS transistor, and more particularly to a MOS transistor for suppressing a short channel effect and a method of fabricating the same.
In recent years, along with the trend of high-integration semiconductor devices such as a dynamic random access memory (DRAM), various problems occur due to the short channel effect in a transistor of a semiconductor device.
As one example of the problems, a general rule of obtaining a threshold voltage independent of a channel length or width is no longer applicable, in particular, to a sub-100 nm channel structure. Accordingly, it is difficult to obtain a desired threshold voltage in a current transistor having a planar structure. Moreover, it is more difficult to obtain the desired threshold voltage in an upcoming transistor having a sub-50 nm channel structure.
As another example of the problems caused by the short channel effect, as the gate width of the transistor of the semiconductor device gets smaller, the density of impurities becomes higher in a contact region and a channel, thereby increasing the intensity of the electric field between a source region and a drain region. The increased intensity of the electric field accelerates electrons between the source region and the drain region to generate a number of hot carriers attacking a gate insulating layer near the drain region. It is known that the hot carriers degrade the electric characteristics of devices. In particular, in the case of semiconductor memory devices such as the DRAM, as the intensity of the electric field between the source region and the drain region increases, leakage current is generated to deteriorate the refresh characteristics of the DRAM.
In compliance with this trend, a variety of transistors having a three-dimensional structure, rather than the planar structure, have been proposed. For example, the transistors having the three-dimensional structure include a transistor having a recess channel and a transistor having a stepped profile. In the transistor having the recess channel, a recess is formed on a semiconductor substrate and a gate is formed in the recess such that the channel is formed along the recess, thereby increasing the effective channel length. In the transistor having the stepped profile, the surface of the active region is formed to have the stepped profile and a gate stack is formed on the stepped profile, thereby increasing the effective channel length while maintaining a constant area of the transistor.
The transistors having the three-dimensional structure including the transistor having the recess channel and the transistor having the stepped profile provide an effect of efficiently suppressing the short channel effect. However, the transistors having the three-dimensional structure have a complicated structure compared to the transistors having the planar gate structure and a method of fabricating the transistors having the three-dimensional structure is also complicated.